1. Field of the Invention
The present invention relates to memory controllers and memory systems.
2. Description of the Related Art
When designing a system including a dynamic random access memory (DRAM), the memory capacity and performance that the system requires are calculated to design a memory controller that can cope with the maximum requirement. Since maximum performance is required for such a memory controller, during the design process the memory controller is designed to have a wide bus, thus increasing the number of external pins of an integrated circuit (IC).
For example, since the resolution of multifunction printers (MFP) has increased, various memory capacities and performances are required for the system. Accordingly, there is a need for memory controllers that can cope with the various system requirements. In the system design process, a memory controller that can cope with the maximum requirement is designed after estimating the required memory capacity and performance.
However, there are cases where, for example, nine out of ten products require a medium memory capacity and performance, while one product requires a large memory capacity and high performance in order to meet its maximum requirement. In such cases, the system is often standardized by designing the ICs to meet the requirements of the large capacity and high performance product (i.e., to have a wide bus width and more external pins).
In the system designed in such a manner, the product requiring the medium or less memory capacity and performance may have a capability exceeding its maximum requirement. An increase in the number of external pins increases not only the cost of the IC itself, but also the cost of the final product. Additionally, power consumption of the IC may unnecessarily increase.
For example, a color copying machine, which employs electrophotographic technologies, having multiple drums, uses a memory for implementing a data output mechanism. In this mechanism, data of multiple colors, simultaneously output from a main memory, is sequentially output at different timings to image processors in the drums. Regarding this mechanism, the capacity of a delay memory that temporarily stores the data undesirably increases.
In addition to the increase in memory capacity, the required performance of the memory controller significantly differs among the various types of copying machine. This results in the presence of a memory controller having a capability that exceeds the maximum requirement or the presence of an IC including the memory controller that has various bus widths.